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library ieee;
use ieee.std_logic_1164.all;
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entity dff is
	port (
		d, clk, rst : in std_logic;
		q : out std_logic;
		);
end dff;
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architecture behavior of dff is
	begin
		process (rst, clk)
		begin
			if (rst= '1') then
				q <= '0';
				elsif (clk 'event and clk = '1') then
					q <= d;
				end if;
			end process;
		end behavior;
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